Zynq-7000 SOC Based Digital Card for Timing and Signal Generation
Zynq-7000 SOC Based Digital card is Developed for the Timing and Signal Generation which provides Interface for digital controls, Analog Parameter Monitoring and Timing Generation required for the TR Module using the Ethernet communication.
- Part Number : FET-TSG-ACP-101
- Lead Time : 4- 8 Weeks
- Device Support : Zynq-7000
The card includes Xilinx’s ZYNQ 7000 series (XC7Z010-2CLG400I) consists of PS system integrates Dual core ARM CortexTM-A9 Processors.
Board is equipped with 256Mbit Quad-SPI Flash chip which is used as Boot Device.
The TSG card is developed to generate the controls and Monitoring signals based on the external clock provided & IPP from External Interface connectors provided.
The TSG card communicate through Ethernet & UART (Debug Configuration).
Length: 138.5mm
Height: 92.6mm
Thickness (+/-5%): 1.6mm
Operating Environmental Temperature: -45°c to +85°c
Configuration
JTAG : Yes
SPI : Yes
QSPI : Yes
UART : Yes
Memory
DDR3 : 4Gb (256M x 16)
Quad-SPI Flash: 128Mb
EEPROM : 4Kb
Control and IO: IO Lines >> 100
Expansion Connectors: D-Sub Connectors >> 2
Clocking : Standard Clock Oscillator >> Yes
Power : +5V Regulator >> Yes
RESOURCES
Featuring Zynq – 7000 Soc based Digital card for Timing and signal Generation – Zynq 700 Soc (XC7Z045-2FFG900I)
Programmable Logic Cells: 28K
Block RAM (36 Kb Blocks): 2.1 Mb (545)
DSP Slices: 900
Look-Up Tables (LUTs): 17,600
Maximum IO Pins: PS IO’s – 128 & PL IO’s – 125
Board of Specifications
Length | 138.5mm |
Height | 92.6mm |
Thickness (+/-5%) | 1.6mm |
Operating Environmental Temperature | -45◦C to +85◦C |
JTAG | Yes |
SPI | Yes |
QSPI | Yes |
UART | Yes |
DDR3 | 4Gb (256M x 16) |
Quad-SPI Flash | 128Mb |
EEPROM | 4Kb |
IO Lines >> 100
D-Sub Connectors >> 2
Standard Clock Oscillator >> Yes
+5V Regulator >> Yes
Resources
Featuring the 4 Channel Data Acquisition Card – Zynq 700 Soc(XC7Z045-2FFG900I)
Programmable Logic Cells | 28K |
Block RAM (36 Kb Blocks) | 2.1 Mb (545) |
DSP Slices | 900 |
Look-Up Tables (LUTs) | 17,600 |
Maximum IO Pins | PS IO’s – 128 PL IO’s – 125 |